Measurement of the Switching Activity of CMOS Digital Circuits at the Gate Level

摘要

Accurate estimation of switching activity is very important indigital circuits. In this paper we present a comparison between the evaluationof the switching activity calculated using logic (Verilog) and electrical(HSPICE) simulators. We also study how the variation on the delay model(min, typ, max) and parasitic effects affect the number of transitions in thecircuit. Results show a variable and significant overestimation of thismeasurement using logic simulators even when including postlayout effects.Furthermore, we show the contribution of glitches to the overall switchingactivity, giving that the treatment of glitches in conventional logic simulatorsis the main cause of switching activity overestimation.